With an increasing demand for higher brightness, the size of semiconductor light-emitting elements (hereinafter referred to as “LED dies” unless specifically designated otherwise) has also been increasing, and light-emitting elements measuring up to 1 mm by 0.5 to 1 mm in area size are commercially available. Since this area size is about the same as that of other chip components such as resistors, there has developed a need for a semiconductor light-emitting device constructed by packaging an LED die in a resin or the like (hereinafter referred to as “LED device” unless specifically designated otherwise) to have about the same area size as the LED die. Such a package is sometimes referred to as a chip size package (hereinafter abbreviated CSP) as it directly reflects the size of the LED die. A CSP has the advantage of small mounting area and a reduced amount of packaging material, and the further advantage of being able to provide greater freedom in the design of lighting equipment, etc., because the number of components to be mounted on the mother substrate can be easily changed according to the required brightness.
FIG. 10 is a cross-sectional view of a light-emitting device 100 (LED device) implemented in CSP form according to a first prior art example.
The light-emitting device 100 shown in FIG. 10 is an ideal form of CSP in which the chip size of the LED die is identical to the outer plan shape of the package, and this LED device is disclosed in patent document 1.
In the LED device 100, a phosphor layer 130 and a lens 132 are formed one on top of the other on the upper surface of a multilayered structure 112c (of semiconductor layers). Seed metals 122a and 122b remaining unetched when a common electrode was formed by electrolytic plating, copper wiring layers 124a and 124b, and columnar copper pillars 126a and 126b formed by electrolytic plating are located on the underside of the multilayered structure 112.
The multilayered structure 112c is made up of a p-type clad layer 112b, a light-emitting layer 112e, and an n-type clad layer 112a. The lower surface of the multilayered structure 112c is covered with an insulating layer 120 having openings in designated portions. Solder balls 136a and 136b are attached to the bottoms of the respective copper pillars 126a and 126b. A reinforcing resin 128 is filled into the space separating the copper pillars 126a and 126b. 
The area size of the LED device 100 shown in FIG. 10 is identical with the area size of the multilayered structure 112c. The LED device 100 is one that is diced from a wafer on which a plurality of LED devices 100 have been produced in a rectangular array; such a package is the smallest one among the group of products categorized as CSPs, and is therefore sometimes referred to as a wafer-level package (WLP). In the LED device 100, since the transparent insulating substrate initially present on the multilayered structure 112c (see FIG. 2 and paragraph 0026 in JP 2001-141176-A) has been removed, light emitted from the light-emitting layer 112e is allowed to emerge only in the upward direction (arrow C). Therefore, the phosphor layer 130 need be provided only on the upper surface of the LED device 100.
In the LED device 100 of FIG. 10, a laser is used to remove the transparent insulating substrate, but this requires large-scale producing equipment and increases the complexity of the producing process. Furthermore, since the phosphor layer 130 is formed on the LED device 100 at the wafer level, it is not possible to address variations in light emission characteristics arising among the individual LED dies produced on the wafer. This leads to the problem that it is difficult to manage the color of emission.